[][src]Module core::arch::arm

🔬 This is a nightly-only experimental API. (stdsimd #27731)
This is supported on ARM only.

Platform-specific intrinsics for the arm platform.

See the module documentation for more details.

Structs

APSRExperimental

Application Program Status Register

ISHExperimental

Inner Shareable is the required shareability domain, reads and writes are the required access types

ISHSTExperimental

Inner Shareable is the required shareability domain, writes are the required access type

NSHExperimental

Non-shareable is the required shareability domain, reads and writes are the required access types

NSHSTExperimental

Non-shareable is the required shareability domain, writes are the required access type

OSHExperimental

Outer Shareable is the required shareability domain, reads and writes are the required access types

OSHSTExperimental

Outer Shareable is the required shareability domain, writes are the required access type

STExperimental

Full system is the required shareability domain, writes are the required access type

SYExperimental

Full system is the required shareability domain, reads and writes are the required access types

float32x2_tExperimental

ARM-specific 64-bit wide vector of two packed f32.

float32x4_tExperimental

ARM-specific 128-bit wide vector of four packed f32.

int8x4_tExperimental

ARM-specific 32-bit wide vector of four packed i8.

int8x8_tExperimental

ARM-specific 64-bit wide vector of eight packed i8.

int8x8x2_tExperimental

ARM-specific type containing two int8x8_t vectors.

int8x8x3_tExperimental

ARM-specific type containing three int8x8_t vectors.

int8x8x4_tExperimental

ARM-specific type containing four int8x8_t vectors.

int8x16_tExperimental

ARM-specific 128-bit wide vector of sixteen packed i8.

int16x2_tExperimental

ARM-specific 32-bit wide vector of two packed i16.

int16x4_tExperimental

ARM-specific 64-bit wide vector of four packed i16.

int16x8_tExperimental

ARM-specific 128-bit wide vector of eight packed i16.

int32x2_tExperimental

ARM-specific 64-bit wide vector of two packed i32.

int32x4_tExperimental

ARM-specific 128-bit wide vector of four packed i32.

int64x1_tExperimental

ARM-specific 64-bit wide vector of one packed i64.

int64x2_tExperimental

ARM-specific 128-bit wide vector of two packed i64.

poly8x8_tExperimental

ARM-specific 64-bit wide polynomial vector of eight packed u8.

poly8x8x2_tExperimental

ARM-specific type containing two poly8x8_t vectors.

poly8x8x3_tExperimental

ARM-specific type containing three poly8x8_t vectors.

poly8x8x4_tExperimental

ARM-specific type containing four poly8x8_t vectors.

poly8x16_tExperimental

ARM-specific 128-bit wide vector of sixteen packed u8.

poly16x4_tExperimental

ARM-specific 64-bit wide vector of four packed u16.

poly16x8_tExperimental

ARM-specific 128-bit wide vector of eight packed u16.

uint8x4_tExperimental

ARM-specific 32-bit wide vector of four packed u8.

uint8x8_tExperimental

ARM-specific 64-bit wide vector of eight packed u8.

uint8x8x2_tExperimental

ARM-specific type containing two uint8x8_t vectors.

uint8x8x3_tExperimental

ARM-specific type containing three uint8x8_t vectors.

uint8x8x4_tExperimental

ARM-specific type containing four uint8x8_t vectors.

uint8x16_tExperimental

ARM-specific 128-bit wide vector of sixteen packed u8.

uint16x2_tExperimental

ARM-specific 32-bit wide vector of two packed u16.

uint16x4_tExperimental

ARM-specific 64-bit wide vector of four packed u16.

uint16x8_tExperimental

ARM-specific 128-bit wide vector of eight packed u16.

uint32x2_tExperimental

ARM-specific 64-bit wide vector of two packed u32.

uint32x4_tExperimental

ARM-specific 128-bit wide vector of four packed u32.

uint64x1_tExperimental

ARM-specific 64-bit wide vector of one packed u64.

uint64x2_tExperimental

ARM-specific 128-bit wide vector of two packed u64.

Functions

__breakpointExperimental

Inserts a breakpoint instruction.

__clrexExperimental

Removes the exclusive lock created by LDREX

__crc32bExperimentalcrc and v8

CRC32 single round checksum for bytes (8 bits).

__crc32cbExperimentalcrc and v8

CRC32-C single round checksum for bytes (8 bits).

__crc32chExperimentalcrc and v8

CRC32-C single round checksum for half words (16 bits).

__crc32cwExperimentalcrc and v8

CRC32-C single round checksum for words (32 bits).

__crc32hExperimentalcrc and v8

CRC32 single round checksum for half words (16 bits).

__crc32wExperimentalcrc and v8

CRC32 single round checksum for words (32 bits).

__dbgExperimental

Generates a DBG instruction.

__dmbExperimental

Generates a DMB (data memory barrier) instruction or equivalent CP15 instruction.

__dsbExperimental

Generates a DSB (data synchronization barrier) instruction or equivalent CP15 instruction.

__isbExperimental

Generates an ISB (instruction synchronization barrier) instruction or equivalent CP15 instruction.

__ldrexExperimental

Executes a exclusive LDR instruction for 32 bit value.

__ldrexbExperimental

Executes a exclusive LDR instruction for 8 bit value.

__ldrexhExperimental

Executes a exclusive LDR instruction for 16 bit value.

__nopExperimental

Generates an unspecified no-op instruction.

__qaddExperimental

Signed saturating addition

__qadd8Experimental

Saturating four 8-bit integer additions

__qadd16Experimental

Saturating two 16-bit integer additions

__qasxExperimental

Returns the 16-bit signed saturated equivalent of

__qdblExperimental

Insert a QADD instruction

__qsaxExperimental

Returns the 16-bit signed saturated equivalent of

__qsubExperimental

Signed saturating subtraction

__qsub8Experimental

Saturating two 8-bit integer subtraction

__qsub16Experimental

Saturating two 16-bit integer subtraction

__rsrExperimental

Reads a 32-bit system register

__rsrpExperimental

Reads a system register containing an address

__sadd8Experimental

Returns the 8-bit signed saturated equivalent of

__sadd16Experimental

Returns the 16-bit signed saturated equivalent of

__sasxExperimental

Returns the 16-bit signed equivalent of

__selExperimental

Select bytes from each operand according to APSR GE flags

__sevExperimental

Generates a SEV (send a global event) hint instruction.

__shadd8Experimental

Signed halving parallel byte-wise addition.

__shadd16Experimental

Signed halving parallel halfword-wise addition.

__shsub8Experimental

Signed halving parallel byte-wise subtraction.

__shsub16Experimental

Signed halving parallel halfword-wise subtraction.

__smlabbExperimental

Insert a SMLABB instruction

__smlabtExperimental

Insert a SMLABT instruction

__smladExperimental

Dual 16-bit Signed Multiply with Addition of products and 32-bit accumulation.

__smlatbExperimental

Insert a SMLATB instruction

__smlattExperimental

Insert a SMLATT instruction

__smlawbExperimental

Insert a SMLAWB instruction

__smlawtExperimental

Insert a SMLAWT instruction

__smlsdExperimental

Dual 16-bit Signed Multiply with Subtraction of products and 32-bit accumulation and overflow detection.

__smuadExperimental

Signed Dual Multiply Add.

__smuadxExperimental

Signed Dual Multiply Add Reversed.

__smulbbExperimental

Insert a SMULBB instruction

__smulbtExperimental

Insert a SMULTB instruction

__smultbExperimental

Insert a SMULTB instruction

__smulttExperimental

Insert a SMULTT instruction

__smulwbExperimental

Insert a SMULWB instruction

__smulwtExperimental

Insert a SMULWT instruction

__smusdExperimental

Signed Dual Multiply Subtract.

__smusdxExperimental

Signed Dual Multiply Subtract Reversed.

__ssub8Experimental

Inserts a SSUB8 instruction.

__strexExperimental

Executes a exclusive STR instruction for 32 bit values

__strexbExperimental

Executes a exclusive STR instruction for 8 bit values

__strexhExperimental

Executes a exclusive STR instruction for 16 bit values

__usad8Experimental

Sum of 8-bit absolute differences.

__usada8Experimental

Sum of 8-bit absolute differences and constant.

__usub8Experimental

Inserts a USUB8 instruction.

__wfeExperimental

Generates a WFE (wait for event) hint instruction, or nothing.

__wfiExperimental

Generates a WFI (wait for interrupt) hint instruction, or nothing.

__wsrExperimental

Writes a 32-bit system register

__wsrpExperimental

Writes a system register containing an address

__yieldExperimental

Generates a YIELD hint instruction.

_clz_u8Experimentalv7

Count Leading Zeros.

_clz_u16Experimentalv7

Count Leading Zeros.

_clz_u32Experimentalv7

Count Leading Zeros.

_rbit_u32Experimentalv7

Reverse the bit order.

_rev_u16Experimental

Reverse the order of the bytes.

_rev_u32Experimental

Reverse the order of the bytes.

udfExperimental

Generates the trap instruction UDF

vabs_s8Experimentalneon and v7

Absolute value (wrapping).

vabs_s16Experimentalneon and v7

Absolute value (wrapping).

vabs_s32Experimentalneon and v7

Absolute value (wrapping).

vabsq_s8Experimentalneon and v7

Absolute value (wrapping).

vabsq_s16Experimentalneon and v7

Absolute value (wrapping).

vabsq_s32Experimentalneon and v7

Absolute value (wrapping).

vadd_f32Experimentalneon and v7

Vector add.

vadd_s8Experimentalneon and v7

Vector add.

vadd_s16Experimentalneon and v7

Vector add.

vadd_s32Experimentalneon and v7

Vector add.

vadd_u8Experimentalneon and v7

Vector add.

vadd_u16Experimentalneon and v7

Vector add.

vadd_u32Experimentalneon and v7

Vector add.

vaddl_s8Experimentalneon and v7

Vector long add.

vaddl_s16Experimentalneon and v7

Vector long add.

vaddl_s32Experimentalneon and v7

Vector long add.

vaddl_u8Experimentalneon and v7

Vector long add.

vaddl_u16Experimentalneon and v7

Vector long add.

vaddl_u32Experimentalneon and v7

Vector long add.

vaddq_f32Experimentalneon and v7

Vector add.

vaddq_s8Experimentalneon and v7

Vector add.

vaddq_s16Experimentalneon and v7

Vector add.

vaddq_s32Experimentalneon and v7

Vector add.

vaddq_s64Experimentalneon and v7

Vector add.

vaddq_u8Experimentalneon and v7

Vector add.

vaddq_u16Experimentalneon and v7

Vector add.

vaddq_u32Experimentalneon and v7

Vector add.

vaddq_u64Experimentalneon and v7

Vector add.

vand_s8Experimentalneon and v7

Vector bitwise and

vand_s16Experimentalneon and v7

Vector bitwise and

vand_s32Experimentalneon and v7

Vector bitwise and

vand_s64Experimentalneon and v7

Vector bitwise and

vand_u8Experimentalneon and v7

Vector bitwise and

vand_u16Experimentalneon and v7

Vector bitwise and

vand_u32Experimentalneon and v7

Vector bitwise and

vand_u64Experimentalneon and v7

Vector bitwise and

vandq_s8Experimentalneon and v7

Vector bitwise and

vandq_s16Experimentalneon and v7

Vector bitwise and

vandq_s32Experimentalneon and v7

Vector bitwise and

vandq_s64Experimentalneon and v7

Vector bitwise and

vandq_u8Experimentalneon and v7

Vector bitwise and

vandq_u16Experimentalneon and v7

Vector bitwise and

vandq_u32Experimentalneon and v7

Vector bitwise and

vandq_u64Experimentalneon and v7

Vector bitwise and

vceq_f32Experimentalneon and v7

Floating-point compare equal

vceq_s8Experimentalneon and v7

Compare bitwise Equal (vector)

vceq_s16Experimentalneon and v7

Compare bitwise Equal (vector)

vceq_s32Experimentalneon and v7

Compare bitwise Equal (vector)

vceq_u8Experimentalneon and v7

Compare bitwise Equal (vector)

vceq_u16Experimentalneon and v7

Compare bitwise Equal (vector)

vceq_u32Experimentalneon and v7

Compare bitwise Equal (vector)

vceqq_f32Experimentalneon and v7

Floating-point compare equal

vceqq_s8Experimentalneon and v7

Compare bitwise Equal (vector)

vceqq_s16Experimentalneon and v7

Compare bitwise Equal (vector)

vceqq_s32Experimentalneon and v7

Compare bitwise Equal (vector)

vceqq_u8Experimentalneon and v7

Compare bitwise Equal (vector)

vceqq_u16Experimentalneon and v7

Compare bitwise Equal (vector)

vceqq_u32Experimentalneon and v7

Compare bitwise Equal (vector)

vcge_f32Experimentalneon and v7

Floating-point compare greater than or equal

vcge_s8Experimentalneon and v7

Compare signed greater than or equal

vcge_s16Experimentalneon and v7

Compare signed greater than or equal

vcge_s32Experimentalneon and v7

Compare signed greater than or equal

vcge_u8Experimentalneon and v7

Compare unsigned greater than or equal

vcge_u16Experimentalneon and v7

Compare unsigned greater than or equal

vcge_u32Experimentalneon and v7

Compare unsigned greater than or equal

vcgeq_f32Experimentalneon and v7

Floating-point compare greater than or equal

vcgeq_s8Experimentalneon and v7

Compare signed greater than or equal

vcgeq_s16Experimentalneon and v7

Compare signed greater than or equal

vcgeq_s32Experimentalneon and v7

Compare signed greater than or equal

vcgeq_u8Experimentalneon and v7

Compare unsigned greater than or equal

vcgeq_u16Experimentalneon and v7

Compare unsigned greater than or equal

vcgeq_u32Experimentalneon and v7

Compare unsigned greater than or equal

vcgt_f32Experimentalneon and v7

Floating-point compare greater than

vcgt_s8Experimentalneon and v7

Compare signed greater than

vcgt_s16Experimentalneon and v7

Compare signed greater than

vcgt_s32Experimentalneon and v7

Compare signed greater than

vcgt_u8Experimentalneon and v7

Compare unsigned highe

vcgt_u16Experimentalneon and v7

Compare unsigned highe

vcgt_u32Experimentalneon and v7

Compare unsigned highe

vcgtq_f32Experimentalneon and v7

Floating-point compare greater than

vcgtq_s8Experimentalneon and v7

Compare signed greater than

vcgtq_s16Experimentalneon and v7

Compare signed greater than

vcgtq_s32Experimentalneon and v7

Compare signed greater than

vcgtq_u8Experimentalneon and v7

Compare unsigned highe

vcgtq_u16Experimentalneon and v7

Compare unsigned highe

vcgtq_u32Experimentalneon and v7

Compare unsigned highe

vcle_f32Experimentalneon and v7

Floating-point compare less than or equal

vcle_s8Experimentalneon and v7

Compare signed less than or equal

vcle_s16Experimentalneon and v7

Compare signed less than or equal

vcle_s32Experimentalneon and v7

Compare signed less than or equal

vcle_u8Experimentalneon and v7

Compare unsigned less than or equal

vcle_u16Experimentalneon and v7

Compare unsigned less than or equal

vcle_u32Experimentalneon and v7

Compare unsigned less than or equal

vcleq_f32Experimentalneon and v7

Floating-point compare less than or equal

vcleq_s8Experimentalneon and v7

Compare signed less than or equal

vcleq_s16Experimentalneon and v7

Compare signed less than or equal

vcleq_s32Experimentalneon and v7

Compare signed less than or equal

vcleq_u8Experimentalneon and v7

Compare unsigned less than or equal

vcleq_u16Experimentalneon and v7

Compare unsigned less than or equal

vcleq_u32Experimentalneon and v7

Compare unsigned less than or equal

vclt_f32Experimentalneon and v7

Floating-point compare less than

vclt_s8Experimentalneon and v7

Compare signed less than

vclt_s16Experimentalneon and v7

Compare signed less than

vclt_s32Experimentalneon and v7

Compare signed less than

vclt_u8Experimentalneon and v7

Compare unsigned less than

vclt_u16Experimentalneon and v7

Compare unsigned less than

vclt_u32Experimentalneon and v7

Compare unsigned less than

vcltq_f32Experimentalneon and v7

Floating-point compare less than

vcltq_s8Experimentalneon and v7

Compare signed less than

vcltq_s16Experimentalneon and v7

Compare signed less than

vcltq_s32Experimentalneon and v7

Compare signed less than

vcltq_u8Experimentalneon and v7

Compare unsigned less than

vcltq_u16Experimentalneon and v7

Compare unsigned less than

vcltq_u32Experimentalneon and v7

Compare unsigned less than

vcvtq_s32_f32Experimentalneon and v7

Floating-point Convert to Signed fixed-point, rounding toward Zero (vector)

vcvtq_u32_f32Experimentalneon and v7

Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector)

vdupq_n_s8Experimentalneon and v7

Duplicate vector element to vector or scalar

vdupq_n_u8Experimentalneon and v7

Duplicate vector element to vector or scalar

veor_s8Experimentalneon and v7

Vector bitwise exclusive or (vector)

veor_s16Experimentalneon and v7

Vector bitwise exclusive or (vector)

veor_s32Experimentalneon and v7

Vector bitwise exclusive or (vector)

veor_s64Experimentalneon and v7

Vector bitwise exclusive or (vector)

veor_u8Experimentalneon and v7

Vector bitwise exclusive or (vector)

veor_u16Experimentalneon and v7

Vector bitwise exclusive or (vector)

veor_u32Experimentalneon and v7

Vector bitwise exclusive or (vector)

veor_u64Experimentalneon and v7

Vector bitwise exclusive or (vector)

veorq_s8Experimentalneon and v7

Vector bitwise exclusive or (vector)

veorq_s16Experimentalneon and v7

Vector bitwise exclusive or (vector)

veorq_s32Experimentalneon and v7

Vector bitwise exclusive or (vector)

veorq_s64Experimentalneon and v7

Vector bitwise exclusive or (vector)

veorq_u8Experimentalneon and v7

Vector bitwise exclusive or (vector)

veorq_u16Experimentalneon and v7

Vector bitwise exclusive or (vector)

veorq_u32Experimentalneon and v7

Vector bitwise exclusive or (vector)

veorq_u64Experimentalneon and v7

Vector bitwise exclusive or (vector)

vextq_s8Experimentalneon and v7

Extract vector from pair of vectors

vextq_u8Experimentalneon and v7

Extract vector from pair of vectors

vget_lane_u8Experimentalneon and v7

Move vector element to general-purpose register

vget_lane_u64Experimentalneon and v7

Move vector element to general-purpose register

vgetq_lane_s32Experimentalneon and v7

Move vector element to general-purpose register

vgetq_lane_u16Experimentalneon and v7

Move vector element to general-purpose register

vgetq_lane_u32Experimentalneon and v7

Move vector element to general-purpose register

vgetq_lane_u64Experimentalneon and v7

Move vector element to general-purpose register

vhadd_s8Experimentalneon and v7

Halving add

vhadd_s16Experimentalneon and v7

Halving add

vhadd_s32Experimentalneon and v7

Halving add

vhadd_u8Experimentalneon and v7

Halving add

vhadd_u16Experimentalneon and v7

Halving add

vhadd_u32Experimentalneon and v7

Halving add

vhaddq_s8Experimentalneon and v7

Halving add

vhaddq_s16Experimentalneon and v7

Halving add

vhaddq_s32Experimentalneon and v7

Halving add

vhaddq_u8Experimentalneon and v7

Halving add

vhaddq_u16Experimentalneon and v7

Halving add

vhaddq_u32Experimentalneon and v7

Halving add

vhsub_s8Experimentalneon and v7

Signed halving subtract

vhsub_s16Experimentalneon and v7

Signed halving subtract

vhsub_s32Experimentalneon and v7

Signed halving subtract

vhsub_u8Experimentalneon and v7

Signed halving subtract

vhsub_u16Experimentalneon and v7

Signed halving subtract

vhsub_u32Experimentalneon and v7

Signed halving subtract

vhsubq_s8Experimentalneon and v7

Signed halving subtract

vhsubq_s16Experimentalneon and v7

Signed halving subtract

vhsubq_s32Experimentalneon and v7

Signed halving subtract

vhsubq_u8Experimentalneon and v7

Signed halving subtract

vhsubq_u16Experimentalneon and v7

Signed halving subtract

vhsubq_u32Experimentalneon and v7

Signed halving subtract

vld1q_dup_f32Experimentalneon and v7

Load one single-element structure and Replicate to all lanes (of one register).

vld1q_f32Experimentalneon and v7

Load multiple single-element structures to one, two, three, or four registers

vld1q_s8Experimentalneon and v7

Load multiple single-element structures to one, two, three, or four registers

vld1q_s32Experimentalneon and v7

Load multiple single-element structures to one, two, three, or four registers

vld1q_u8Experimentalneon and v7

Load multiple single-element structures to one, two, three, or four registers

vld1q_u32Experimentalneon and v7

Load multiple single-element structures to one, two, three, or four registers

vmaxq_f32Experimentalneon and v7

Floating-point maxmimum (vector).

vminq_f32Experimentalneon and v7

Floating-point minimum (vector).

vmovl_s8Experimentalneon and v7

Vector long move.

vmovl_s16Experimentalneon and v7

Vector long move.

vmovl_s32Experimentalneon and v7

Vector long move.

vmovl_u8Experimentalneon and v7

Vector long move.

vmovl_u16Experimentalneon and v7

Vector long move.

vmovl_u32Experimentalneon and v7

Vector long move.

vmovn_s16Experimentalneon and v7

Vector narrow integer.

vmovn_s32Experimentalneon and v7

Vector narrow integer.

vmovn_s64Experimentalneon and v7

Vector narrow integer.

vmovn_u16Experimentalneon and v7

Vector narrow integer.

vmovn_u32Experimentalneon and v7

Vector narrow integer.

vmovn_u64Experimentalneon and v7

Vector narrow integer.

vmovq_n_u8Experimentalneon and v7

Duplicate vector element to vector or scalar

vmul_f32Experimentalneon and v7

Multiply

vmul_s8Experimentalneon and v7

Multiply

vmul_s16Experimentalneon and v7

Multiply

vmul_s32Experimentalneon and v7

Multiply

vmul_u8Experimentalneon and v7

Multiply

vmul_u16Experimentalneon and v7

Multiply

vmul_u32Experimentalneon and v7

Multiply

vmulq_f32Experimentalneon and v7

Multiply

vmulq_s8Experimentalneon and v7

Multiply

vmulq_s16Experimentalneon and v7

Multiply

vmulq_s32Experimentalneon and v7

Multiply

vmulq_u8Experimentalneon and v7

Multiply

vmulq_u16Experimentalneon and v7

Multiply

vmulq_u32Experimentalneon and v7

Multiply

vmvn_p8Experimentalneon and v7

Vector bitwise not.

vmvn_s8Experimentalneon and v7

Vector bitwise not.

vmvn_s16Experimentalneon and v7

Vector bitwise not.

vmvn_s32Experimentalneon and v7

Vector bitwise not.

vmvn_u8Experimentalneon and v7

Vector bitwise not.

vmvn_u16Experimentalneon and v7

Vector bitwise not.

vmvn_u32Experimentalneon and v7

Vector bitwise not.

vmvnq_p8Experimentalneon and v7

Vector bitwise not.

vmvnq_s8Experimentalneon and v7

Vector bitwise not.

vmvnq_s16Experimentalneon and v7

Vector bitwise not.

vmvnq_s32Experimentalneon and v7

Vector bitwise not.

vmvnq_u8Experimentalneon and v7

Vector bitwise not.

vmvnq_u16Experimentalneon and v7

Vector bitwise not.

vmvnq_u32Experimentalneon and v7

Vector bitwise not.

vorr_s8Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorr_s16Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorr_s32Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorr_s64Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorr_u8Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorr_u16Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorr_u32Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorr_u64Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorrq_s8Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorrq_s16Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorrq_s32Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorrq_s64Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorrq_u8Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorrq_u16Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorrq_u32Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vorrq_u64Experimentalneon and v7

Vector bitwise or (immediate, inclusive)

vpadd_s8Experimentalneon and v7

Add pairwise.

vpadd_s16Experimentalneon and v7

Add pairwise.

vpadd_s32Experimentalneon and v7

Add pairwise.

vpadd_u8Experimentalneon and v7

Add pairwise.

vpadd_u16Experimentalneon and v7

Add pairwise.

vpadd_u32Experimentalneon and v7

Add pairwise.

vpmax_f32Experimentalneon and v7

Folding maximum of adjacent pairs

vpmax_s8Experimentalneon and v7

Folding maximum of adjacent pairs

vpmax_s16Experimentalneon and v7

Folding maximum of adjacent pairs

vpmax_s32Experimentalneon and v7

Folding maximum of adjacent pairs

vpmax_u8Experimentalneon and v7

Folding maximum of adjacent pairs

vpmax_u16Experimentalneon and v7

Folding maximum of adjacent pairs

vpmax_u32Experimentalneon and v7

Folding maximum of adjacent pairs

vpmin_f32Experimentalneon and v7

Folding minimum of adjacent pairs

vpmin_s8Experimentalneon and v7

Folding minimum of adjacent pairs

vpmin_s16Experimentalneon and v7

Folding minimum of adjacent pairs

vpmin_s32Experimentalneon and v7

Folding minimum of adjacent pairs

vpmin_u8Experimentalneon and v7

Folding minimum of adjacent pairs

vpmin_u16Experimentalneon and v7

Folding minimum of adjacent pairs

vpmin_u32Experimentalneon and v7

Folding minimum of adjacent pairs

vqadd_s8Experimentalneon and v7

Saturating add

vqadd_s16Experimentalneon and v7

Saturating add

vqadd_s32Experimentalneon and v7

Saturating add

vqadd_u8Experimentalneon and v7

Saturating add

vqadd_u16Experimentalneon and v7

Saturating add

vqadd_u32Experimentalneon and v7

Saturating add

vqaddq_s8Experimentalneon and v7

Saturating add

vqaddq_s16Experimentalneon and v7

Saturating add

vqaddq_s32Experimentalneon and v7

Saturating add

vqaddq_u8Experimentalneon and v7

Saturating add

vqaddq_u16Experimentalneon and v7

Saturating add

vqaddq_u32Experimentalneon and v7

Saturating add

vqmovn_u64Experimentalneon and v7

Unsigned saturating extract narrow.

vqsub_s8Experimentalneon and v7

Saturating subtract

vqsub_s16Experimentalneon and v7

Saturating subtract

vqsub_s32Experimentalneon and v7

Saturating subtract

vqsub_u8Experimentalneon and v7

Saturating subtract

vqsub_u16Experimentalneon and v7

Saturating subtract

vqsub_u32Experimentalneon and v7

Saturating subtract

vqsubq_s8Experimentalneon and v7

Saturating subtract

vqsubq_s16Experimentalneon and v7

Saturating subtract

vqsubq_s32Experimentalneon and v7

Saturating subtract

vqsubq_u8Experimentalneon and v7

Saturating subtract

vqsubq_u16Experimentalneon and v7

Saturating subtract

vqsubq_u32Experimentalneon and v7

Saturating subtract

vreinterpret_u64_u32Experimentalneon and v7

Vector reinterpret cast operation

vreinterpretq_s8_u8Experimentalneon and v7

Vector reinterpret cast operation

vreinterpretq_u8_s8Experimentalneon and v7

Vector reinterpret cast operation

vreinterpretq_u16_u8Experimentalneon and v7

Vector reinterpret cast operation

vreinterpretq_u32_u8Experimentalneon and v7

Vector reinterpret cast operation

vreinterpretq_u64_u8Experimentalneon and v7

Vector reinterpret cast operation

vrhadd_s8Experimentalneon and v7

Rounding halving add

vrhadd_s16Experimentalneon and v7

Rounding halving add

vrhadd_s32Experimentalneon and v7

Rounding halving add

vrhadd_u8Experimentalneon and v7

Rounding halving add

vrhadd_u16Experimentalneon and v7

Rounding halving add

vrhadd_u32Experimentalneon and v7

Rounding halving add

vrhaddq_s8Experimentalneon and v7

Rounding halving add

vrhaddq_s16Experimentalneon and v7

Rounding halving add

vrhaddq_s32Experimentalneon and v7

Rounding halving add

vrhaddq_u8Experimentalneon and v7

Rounding halving add

vrhaddq_u16Experimentalneon and v7

Rounding halving add

vrhaddq_u32Experimentalneon and v7

Rounding halving add

vrsqrte_f32Experimentalneon

Reciprocal square-root estimate.

vshlq_n_u8Experimentalneon and v7

Shift right

vshrq_n_u8Experimentalneon and v7

Unsigned shift right

vsub_f32Experimentalneon and v7

Subtract

vsub_s8Experimentalneon and v7

Subtract

vsub_s16Experimentalneon and v7

Subtract

vsub_s32Experimentalneon and v7

Subtract

vsub_s64Experimentalneon and v7

Subtract

vsub_u8Experimentalneon and v7

Subtract

vsub_u16Experimentalneon and v7

Subtract

vsub_u32Experimentalneon and v7

Subtract

vsub_u64Experimentalneon and v7

Subtract

vsubq_f32Experimentalneon and v7

Subtract

vsubq_s8Experimentalneon and v7

Subtract

vsubq_s16Experimentalneon and v7

Subtract

vsubq_s32Experimentalneon and v7

Subtract

vsubq_s64Experimentalneon and v7

Subtract

vsubq_u8Experimentalneon and v7

Subtract

vsubq_u16Experimentalneon and v7

Subtract

vsubq_u32Experimentalneon and v7

Subtract

vsubq_u64Experimentalneon and v7

Subtract

vtbl1_p8Experimentalneon,v7

Table look-up

vtbl1_s8Experimentalneon,v7

Table look-up

vtbl1_u8Experimentalneon,v7

Table look-up

vtbl2_p8Experimentalneon,v7

Table look-up

vtbl2_s8Experimentalneon,v7

Table look-up

vtbl2_u8Experimentalneon,v7

Table look-up

vtbl3_p8Experimentalneon,v7

Table look-up

vtbl3_s8Experimentalneon,v7

Table look-up

vtbl3_u8Experimentalneon,v7

Table look-up

vtbl4_p8Experimentalneon,v7

Table look-up

vtbl4_s8Experimentalneon,v7

Table look-up

vtbl4_u8Experimentalneon,v7

Table look-up

vtbx1_p8Experimentalneon,v7

Extended table look-up

vtbx1_s8Experimentalneon,v7

Extended table look-up

vtbx1_u8Experimentalneon,v7

Extended table look-up

vtbx2_p8Experimentalneon,v7

Extended table look-up

vtbx2_s8Experimentalneon,v7

Extended table look-up

vtbx2_u8Experimentalneon,v7

Extended table look-up

vtbx3_p8Experimentalneon,v7

Extended table look-up

vtbx3_s8Experimentalneon,v7

Extended table look-up

vtbx3_u8Experimentalneon,v7

Extended table look-up

vtbx4_p8Experimentalneon,v7

Extended table look-up

vtbx4_s8Experimentalneon,v7

Extended table look-up

vtbx4_u8Experimentalneon,v7

Extended table look-up